The present invention relates to electrical interconnects for printed circuit boards.
When the space available for signal traces on printed circuit boards (xe2x80x9cPCBsxe2x80x9d) is limited, signal lines for connecting components may have to be routed along more than one PCB layer. Some of those signal lines may run along the surface of the PCB. Others, as shown in FIG. 1, may run from a signal transmitting component (represented by line 1), which is mounted onto first layer 2 of PCB 10, through via 9 to signal trace 4, which runs along second layer 5. Via 9""s inductance and capacitance characteristics introduce a time delay. As 15 a consequence, signals driven along the surface of PCB 10 are skewed with respect to signals routed through via 9 and signal trace 4. For source synchronous interconnects, such skew may result when clock and data signals (or consecutive data signals) take different paths across the PCB.
Although this may be a third or fourth order effect for relatively low speed interconnects, such skew can effectively limit the maximum frequency at which high speed, pipelined electrical signals may be driven along a high speed interconnect. Take, for example, the Direct Rambus memory channel, which a PCB may include for transmitting 300 MHz, or higher, clock signals, in a pipelined fashion, between a memory controller and a memory module. (Because data is taken off both the falling and rising edges of the clock signal, the data transfer rate may be 600M transfers, or more.) For PCBs having two RIMMS, the Direct Rambus memory channel can require signals to pass through 6 viasxe2x80x942 each located between the memory controller and the first RIMM, between the two RIMMs, and between the second RIMM and the termination resistor. (One via routes signals from the transmitting component to a second PCB layer, and another via routes signals from that layer to the component that will receive the signals.) When signals that are transmitted between two components must pass through multiple vias, the timing skew that accumulates over the length of the connection, resulting from the additive effect of the time delay that each via generates, may limit the frequency at which the interconnect may operate.
Accordingly, there is a need for an improved interconnect for a printed circuit board. There is a need for such an interconnect to reduce skew between signals driven along a PCB layer and signals driven along at least two PCB layers that are connected by a via. The present invention provides such an interconnect.